62 lines
1.7 KiB
Nix
62 lines
1.7 KiB
Nix
{ lib, stdenv, fetchFromGitHub
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, python3, boost
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, cmake
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}:
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stdenv.mkDerivation rec {
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pname = "trellis";
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version = "2021.01.02";
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# git describe --tags
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realVersion = with lib; with builtins;
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"1.0-482-g${substring 0 7 (elemAt srcs 0).rev}";
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srcs = [
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(fetchFromGitHub {
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owner = "YosysHQ";
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repo = "prjtrellis";
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rev = "60c05b3f4e71fd78d4fba5c31f9974694245199e";
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sha256 = "1k37mxwxv9fpm6xnrxlqqap7zqh2dvgqncphj3asi2rz0kh07ppf";
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name = "trellis";
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})
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(fetchFromGitHub {
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owner = "YosysHQ";
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repo = "prjtrellis-db";
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rev = "2cf058e7a3ba36134d21e34823e9b2ecaaceac2c";
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sha256 = "1hjaw5jkwiaiznm2z0smy88m2cdz63cd51z4nibajfih7ikvkj6g";
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name = "trellis-database";
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})
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];
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sourceRoot = "trellis";
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buildInputs = [ boost ];
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nativeBuildInputs = [ cmake python3 ];
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cmakeFlags = [
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"-DCURRENT_GIT_VERSION=${realVersion}"
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# TODO: should this be in stdenv instead?
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"-DCMAKE_INSTALL_DATADIR=${placeholder "out"}/share"
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];
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preConfigure = with builtins; ''
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rmdir database && ln -sfv ${elemAt srcs 1} ./database
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source environment.sh
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cd libtrellis
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'';
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meta = with lib; {
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description = "Documentation and bitstream tools for Lattice ECP5 FPGAs";
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longDescription = ''
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Project Trellis documents the Lattice ECP5 architecture
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to enable development of open-source tools. Its goal is
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to provide sufficient information to develop a free and
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open Verilog to bitstream toolchain for these devices.
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'';
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homepage = "https://github.com/SymbiFlow/prjtrellis";
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license = lib.licenses.isc;
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maintainers = with maintainers; [ q3k thoughtpolice emily ];
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platforms = lib.platforms.all;
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};
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}
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