2015-12-29 16:30:45 +00:00
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{ stdenv, fetchFromGitHub, icestorm }:
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2018-02-14 06:15:34 +00:00
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with builtins;
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2015-12-29 16:30:45 +00:00
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stdenv.mkDerivation rec {
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name = "arachne-pnr-${version}";
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2018-03-08 00:33:35 +00:00
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version = "2018.03.07";
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2015-12-29 16:30:45 +00:00
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src = fetchFromGitHub {
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2017-11-05 17:28:41 +00:00
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owner = "cseed";
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repo = "arachne-pnr";
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2018-03-08 00:33:35 +00:00
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rev = "6701132cbd5c7b31edd0ff18ca6727eb3691186b";
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sha256 = "1c55k9gpq042mkyxrblwskbmr3v0baj4gkwm45v1gvmhdza6gfw8";
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2015-12-29 16:30:45 +00:00
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};
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2017-10-17 12:11:00 +01:00
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enableParallelBuilding = true;
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2017-10-16 08:29:21 +01:00
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makeFlags =
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2018-02-14 06:15:34 +00:00
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[ "PREFIX=$(out)"
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"ICEBOX=${icestorm}/share/icebox"
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2017-10-16 08:29:21 +01:00
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];
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2015-12-29 16:30:45 +00:00
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2018-02-14 06:15:34 +00:00
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patchPhase = ''
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substituteInPlace ./Makefile \
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--replace 'echo UNKNOWN' 'echo ${substring 0 10 src.rev}'
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'';
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2015-12-29 16:30:45 +00:00
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meta = {
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description = "Place and route tool for FPGAs";
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longDescription = ''
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Arachne-pnr implements the place and route step of
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the hardware compilation process for FPGAs. It
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accepts as input a technology-mapped netlist in BLIF
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format, as output by the Yosys [0] synthesis suite
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for example. It currently targets the Lattice
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Semiconductor iCE40 family of FPGAs [1]. Its output
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is a textual bitstream representation for assembly by
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the IceStorm [2] icepack command.
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'';
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homepage = https://github.com/cseed/arachne-pnr;
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2017-09-02 10:02:52 +01:00
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license = stdenv.lib.licenses.mit;
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2017-10-16 08:29:21 +01:00
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maintainers = with stdenv.lib.maintainers; [ shell thoughtpolice ];
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2016-08-02 18:50:55 +01:00
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platforms = stdenv.lib.platforms.linux;
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2015-12-29 16:30:45 +00:00
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};
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}
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