46 lines
958 B
VHDL
46 lines
958 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_MISC.or_reduce;
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entity simple is
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port (
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CLK, RESET : in std_ulogic;
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DATA_OUT : out std_ulogic_vector(7 downto 0);
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DONE_OUT : out std_ulogic
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);
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end simple;
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architecture beh of simple is
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signal data : std_ulogic_vector(7 downto 0);
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signal done: std_ulogic;
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begin
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proc_ctr : process(CLK)
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begin
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if (CLK = '1' and CLK'event) then
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if (RESET = '1') then
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data <= "01011111";
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done <= '0';
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else
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case data is
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when "00100000" => data <= "01001110";
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when "01001110" => data <= "01101001";
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when "01101001" => data <= "01111000";
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when "01111000" => data <= "01001111";
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when "01001111" => data <= "01010011";
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when others => data <= "00100000";
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end case;
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done <= not or_reduce(data xor "01010011");
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end if;
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end if;
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end process;
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DATA_OUT <= data;
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DONE_OUT <= done;
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end beh;
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